Embedded FIR filter design for real-time refocusing using a standard plenoptic video camera
| dc.contributor.author | Hahne, Christopher | en |
| dc.contributor.author | Aggoun, Amar | en |
| dc.date.accessioned | 2014-02-21T11:31:36Z | |
| dc.date.available | 2014-02-21T11:31:36Z | |
| dc.date.issued | 2014-02-03 | |
| dc.identifier.citation | Hahne, C. and Aggoun, A. (2014) “Embedded FIR filter Design for Real-Time Refocusing Using a Standard Plenoptic Video Camera” in [IS&T/SPIE Digital Photography X], Proc. SPIE 9023, 4, San Francisco, CA, 2014. | en |
| dc.identifier.doi | 10.1117/12.2042495 | |
| dc.identifier.uri | http://hdl.handle.net/10547/313167 | |
| dc.description | Copyright 2014 Society of Photo-Optical Instrumentation Engineers and IS&T—The Society for Imaging Science and Technology. One print or electronic copy may be made for personal use only. Systematic reproduction and distribution, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited. | en |
| dc.description.abstract | A novel and low-cost embedded hardware architecture for real-time refocusing based on a standard plenoptic camera is presented in this study. The proposed layout design synthesizes refocusing slices directly from micro images by omitting the process for the commonly used sub-aperture extraction. Therefore, intellectual property cores, containing switch controlled Finite Impulse Response (FIR) filters, are developed and applied to the Field Programmable Gate Array (FPGA) XC6SLX45 from Xilinx. Enabling the hardware design to work economically, the FIR filters are composed of stored product as well as upsampling and interpolation techniques in order to achieve an ideal relation between image resolution, delay time, power consumption and the demand of logic gates. The video output is transmitted via High-Definition Multimedia Interface (HDMI) with a resolution of 720p at a frame rate of 60 fps conforming to the HD ready standard. Examples of the synthesized refocusing slices are presented. | |
| dc.language.iso | en_US | en |
| dc.publisher | SPIE - the international society for optics and photonics | en |
| dc.relation.ispartofseries | 9023 | en |
| dc.relation.ispartofseries | 4 | en |
| dc.relation.url | http://spie.org/Publications/Proceedings/Paper/10.1117/12.2042495 | |
| dc.rights | An error occurred on the license name. | * |
| dc.rights.uri | An error occurred getting the license - uri. | * |
| dc.subject | light field | en |
| dc.subject | plenoptic camera | en |
| dc.subject | refocusing | en |
| dc.subject | ray tracing | en |
| dc.subject | hardware | en |
| dc.subject | signal processing | en |
| dc.subject | FPGA | en |
| dc.subject | FIR filter | en |
| dc.title | Embedded FIR filter design for real-time refocusing using a standard plenoptic video camera | en_US |
| dc.type | Conference papers, meetings and proceedings | en |
| dc.contributor.department | University of Bedfordshire | en |
| html.description.abstract | A novel and low-cost embedded hardware architecture for real-time refocusing based on a standard plenoptic camera is presented in this study. The proposed layout design synthesizes refocusing slices directly from micro images by omitting the process for the commonly used sub-aperture extraction. Therefore, intellectual property cores, containing switch controlled Finite Impulse Response (FIR) filters, are developed and applied to the Field Programmable Gate Array (FPGA) XC6SLX45 from Xilinx. Enabling the hardware design to work economically, the FIR filters are composed of stored product as well as upsampling and interpolation techniques in order to achieve an ideal relation between image resolution, delay time, power consumption and the demand of logic gates. The video output is transmitted via High-Definition Multimedia Interface (HDMI) with a resolution of 720p at a frame rate of 60 fps conforming to the HD ready standard. Examples of the synthesized refocusing slices are presented. |
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