SpiNNaker: a multi-core System-on-Chip for massively-parallel neural net simulation
dc.contributor.author | Painkras, Eustace | en_GB |
dc.contributor.author | Plana, Luis A. | en_GB |
dc.contributor.author | Garside, Jim D. | en_GB |
dc.contributor.author | Temple, Steve | en_GB |
dc.contributor.author | Davidson, Simon | en_GB |
dc.contributor.author | Pepper, Jeffrey | en_GB |
dc.contributor.author | Clark, David | en_GB |
dc.contributor.author | Patterson, Cameron | en_GB |
dc.contributor.author | Furber, Steve B. | en_GB |
dc.date.accessioned | 2013-08-12T08:18:04Z | |
dc.date.available | 2013-08-12T08:18:04Z | |
dc.date.issued | 2012 | |
dc.identifier.citation | Painkras, E., Plana, L.A., Garside, J. et al, (2012) 'SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation', IEEE Custom Integrated Circuits Conference (CICC), pp.1-4 | en_GB |
dc.identifier.doi | 10.1109/CICC.2012.6330636 | |
dc.identifier.uri | http://hdl.handle.net/10547/297903 | |
dc.description.abstract | The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements. | |
dc.language.iso | en | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | en_GB |
dc.relation.url | http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6330636 | en_GB |
dc.subject | digital simulation | en_GB |
dc.subject | microprocessor chips | en_GB |
dc.subject | neural nets | en_GB |
dc.subject | parallel processing | en_GB |
dc.subject | system-on-chip | en_GB |
dc.title | SpiNNaker: a multi-core System-on-Chip for massively-parallel neural net simulation | en |
dc.type | Conference papers, meetings and proceedings | en |
html.description.abstract | The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements. |