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dc.contributor.authorPlana, Luis A.en_GB
dc.contributor.authorClark, Daviden_GB
dc.contributor.authorDavidson, Simonen_GB
dc.contributor.authorFurber, Steve B.en_GB
dc.contributor.authorGarside, Jim D.en_GB
dc.contributor.authorPainkras, Eustaceen_GB
dc.contributor.authorPepper, Jeffreyen_GB
dc.contributor.authorTemple, Steveen_GB
dc.contributor.authorBainbridge, Johnen_GB
dc.date.accessioned2013-04-07T17:28:50Z
dc.date.available2013-04-07T17:28:50Z
dc.date.issued2011
dc.identifier.citationPlana, L.; Clark, D.; Davidson, S.; Furber, S.; Garside, J.; Painkras, E.; Pepper, E.; Temple, S. and Bainbridge, J. (2011) 'SpiNNaker: Design and Implementation of a GALS Multi-Core System-on-Chip' 7 (4), article 17:1-17 ACM Journal on Emerging Technologies in Computing Systemsen_GB
dc.identifier.issn15504832
dc.identifier.doi10.1145/2043643.2043647
dc.identifier.urihttp://hdl.handle.net/10547/279165
dc.description.abstractThe design and implementation of Globally Asynchronous Locally Synchronous Systems-on-Chip is a challenging activity. The large size and complexity of the systems require the use of Computer-Aided Design (CAD) tools but, unfortunately, most tools do not work adequately with asynchronous circuits. This paper describes the successful design and implementation of SpiNNaker, a GALS multi-core system-on-chip. The processes was completed using commercial CAD tools from synthesis to layout. A hierarchical methodology was devised to deal with the asynchronous sections of the system, encapsulating and validating timing assumptions at each level. The crossbar topology combined with a pipelined asynchronous fabric implementation allows the on-chip network to meet the stringent requirements of the system. The implementation methodology constrains the design in a way which allows the tools to complete their tasks successfully. A first test chip, with reduced resources and complexity was taped-out using the proposed methodology. Test chips were received in December 2009 and were fully functional. The methodology had to be modified to cope with the increased complexity of the SpiNNaker SoC. SpiNNaker chips were delivered in May 2011 and were also fully operational, and the interconnect requirements were met.
dc.language.isoenen
dc.publisherACMen_GB
dc.relation.urlhttp://dl.acm.org/citation.cfm?doid=2043643.2043647en_GB
dc.subjectasynchronous systemen_GB
dc.subjectnetwork-on-chipen_GB
dc.titleSpiNNaker: design and implementation of a GALS multicore system-on-chipen
dc.typeArticleen
dc.identifier.journalACM Journal on Emerging Technologies in Computing Systemsen_GB
html.description.abstractThe design and implementation of Globally Asynchronous Locally Synchronous Systems-on-Chip is a challenging activity. The large size and complexity of the systems require the use of Computer-Aided Design (CAD) tools but, unfortunately, most tools do not work adequately with asynchronous circuits. This paper describes the successful design and implementation of SpiNNaker, a GALS multi-core system-on-chip. The processes was completed using commercial CAD tools from synthesis to layout. A hierarchical methodology was devised to deal with the asynchronous sections of the system, encapsulating and validating timing assumptions at each level. The crossbar topology combined with a pipelined asynchronous fabric implementation allows the on-chip network to meet the stringent requirements of the system. The implementation methodology constrains the design in a way which allows the tools to complete their tasks successfully. A first test chip, with reduced resources and complexity was taped-out using the proposed methodology. Test chips were received in December 2009 and were fully functional. The methodology had to be modified to cope with the increased complexity of the SpiNNaker SoC. SpiNNaker chips were delivered in May 2011 and were also fully operational, and the interconnect requirements were met.


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