Cache-oblivious matrix algorithms in the age of multicores and many cores
Issue Date
2012Subjects
shared-memory platformscache oblivious
block recursive
linear algebra
performance
parallelization
Metadata
Show full item recordAbstract
This article highlights the issue of upcoming wider single-instruction, multiple-data units as well as steadily increasing core counts on contemporary and future processor architectures. We present the recent port to and latest results of cache-oblivious algorithms and implementations of our TifaMMy code on four architectures: SGI's UltraViolet distributed shared-memory machine, Intel's latest x86 architecture code-named Sandy Bridge, AMD's new Bulldozer architecture, and Intel's future Many Integrated Core architecture. TifaMMy's matrix multiplication and LU decomposition routines have been adapted and tuned with regard to these architectures. Results are discussed and compared with vendors’ architecture-specific and optimized libraries, Math Kernel Library and AMD Core Math Library, for both a standard C++ version with vectorization compiler switches and TifaMMy's highly optimized vector intrinsics version. We provide insights into architectural properties and comment on the feasibility of heterogeneous cores and accelerators, namely graphics processing units. Besides bare-metal performance, the test platforms’ ease of use is analyzed in detail, and the portability of our approach to new and upcoming silicon is discussed with regard to required effort on code change abstraction levels.Citation
Heinecke, A. and Trinitis, C. (2012), 'Cache-oblivious matrix algorithms in the age of multicores and many cores'. Concurrency Computat.: Pract. Exper.. doi: 10.1002/cpe.2974Publisher
John Wiley & SonsDOI
10.1002/cpe.2974Additional Links
http://doi.wiley.com/10.1002/cpe.2974Type
ArticleLanguage
enISSN
15320626ae974a485f413a2113503eed53cd6c53
10.1002/cpe.2974