Sparse matrix operations on several multi-core architectures
| dc.contributor.author | Trinitis, Carsten | en_GB |
| dc.contributor.author | Küstner, Tilman | en_GB |
| dc.contributor.author | Weidendorfer, Josef | en_GB |
| dc.contributor.author | Smajic, Jasmin | en_GB |
| dc.date.accessioned | 2012-11-05T09:45:43Z | en |
| dc.date.available | 2012-11-05T09:45:43Z | en |
| dc.date.issued | 2010 | en |
| dc.identifier.citation | Trinitis, C. et al (2010) 'Sparse matrix operations on several multi-core architectures' The Journal of Supercomputing 57 (2):132-140 | en_GB |
| dc.identifier.issn | 0920-8542 | en |
| dc.identifier.issn | 1573-0484 | en |
| dc.identifier.doi | 10.1007/s11227-010-0428-9 | en |
| dc.identifier.uri | http://hdl.handle.net/10547/250939 | en |
| dc.description | From the issue entitled "Special Issue on Parallel Computing Technologies" | en_GB |
| dc.description.abstract | This paper compares various contemporary multicore-based microprocessor architectures from different vendors with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix decomposition is used as a benchmark application. The example matrix used in the experiments comes from an electrical engineering application, where numerical simulation of physical processes plays an important role in the design of industrial products. Within this context, thread-to-core pinning and cache optimization are two important aspects which are investigated in more detail. | |
| dc.language.iso | en | en |
| dc.publisher | SpringerLink | en_GB |
| dc.relation.url | http://www.springerlink.com/index/10.1007/s11227-010-0428-9 | en_GB |
| dc.subject | multicore | en_GB |
| dc.subject | pinning | en_GB |
| dc.subject | cache optimization | en_GB |
| dc.subject | performance optimization | en_GB |
| dc.subject | sparse matrices | en_GB |
| dc.title | Sparse matrix operations on several multi-core architectures | en |
| dc.type | Article | en |
| dc.identifier.journal | The Journal of Supercomputing | en_GB |
| html.description.abstract | This paper compares various contemporary multicore-based microprocessor architectures from different vendors with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix decomposition is used as a benchmark application. The example matrix used in the experiments comes from an electrical engineering application, where numerical simulation of physical processes plays an important role in the design of industrial products. Within this context, thread-to-core pinning and cache optimization are two important aspects which are investigated in more detail. |