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AbstractThis paper compares various contemporary multicore-based microprocessor architectures from different vendors with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix decomposition is used as a benchmark application. The example matrix used in the experiments comes from an electrical engineering application, where numerical simulation of physical processes plays an important role in the design of industrial products. Within this context, thread-to-core pinning and cache optimization are two important aspects which are investigated in more detail.
CitationTrinitis, C. et al (2010) 'Sparse matrix operations on several multi-core architectures' The Journal of Supercomputing 57 (2):132-140
JournalThe Journal of Supercomputing
DescriptionFrom the issue entitled "Special Issue on Parallel Computing Technologies"