Abstract
This paper compares various contemporary multicore-based microprocessor architectures from different vendors with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix decomposition is used as a benchmark application. The example matrix used in the experiments comes from an electrical engineering application, where numerical simulation of physical processes plays an important role in the design of industrial products. Within this context, thread-to-core pinning and cache optimization are two important aspects which are investigated in more detail.Citation
Trinitis, C. et al (2010) 'Sparse matrix operations on several multi-core architectures' The Journal of Supercomputing 57 (2):132-140Publisher
SpringerLinkJournal
The Journal of SupercomputingAdditional Links
http://www.springerlink.com/index/10.1007/s11227-010-0428-9Type
ArticleLanguage
enDescription
From the issue entitled "Special Issue on Parallel Computing Technologies"ISSN
0920-85421573-0484
ae974a485f413a2113503eed53cd6c53
10.1007/s11227-010-0428-9