2.50
Hdl Handle:
http://hdl.handle.net/10547/593703
Title:
SpiNNaker: a 1-W 18-core system-on-chip for massively-parallel neural network simulation
Authors:
Painkras, Eustace; Plana, Luis A.; Garside, Jim; Temple, Steve; Galluppi, Francesco; Patterson, Cameron; Lester, David R.; Brown, Andrew D.; Furber, Steve B.
Abstract:
The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural Network architecture - is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm2 die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements.
Affiliation:
University of Manchester
Citation:
Painkras, E. et al (2013) 'SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation' IEEE Journal of Solid-State Circuits 48 (8):1943
Publisher:
IEEE
Journal:
IEEE Journal of Solid-State Circuits
Issue Date:
Aug-2013
URI:
http://hdl.handle.net/10547/593703
DOI:
10.1109/JSSC.2013.2259038
Additional Links:
http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6515159; http://eprints.soton.ac.uk/350493/
Type:
Article
Language:
en
ISSN:
0018-9200; 1558-173X
Appears in Collections:
Centre for Research in Distributed Technologies (CREDIT)

Full metadata record

DC FieldValue Language
dc.contributor.authorPainkras, Eustaceen
dc.contributor.authorPlana, Luis A.en
dc.contributor.authorGarside, Jimen
dc.contributor.authorTemple, Steveen
dc.contributor.authorGalluppi, Francescoen
dc.contributor.authorPatterson, Cameronen
dc.contributor.authorLester, David R.en
dc.contributor.authorBrown, Andrew D.en
dc.contributor.authorFurber, Steve B.en
dc.date.accessioned2016-01-18T12:47:38Zen
dc.date.available2016-01-18T12:47:38Zen
dc.date.issued2013-08en
dc.identifier.citationPainkras, E. et al (2013) 'SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation' IEEE Journal of Solid-State Circuits 48 (8):1943en
dc.identifier.issn0018-9200en
dc.identifier.issn1558-173Xen
dc.identifier.doi10.1109/JSSC.2013.2259038en
dc.identifier.urihttp://hdl.handle.net/10547/593703en
dc.description.abstractThe modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural Network architecture - is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm2 die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements.en
dc.language.isoenen
dc.publisherIEEEen
dc.relation.urlhttp://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6515159en
dc.relation.urlhttp://eprints.soton.ac.uk/350493/en
dc.rightsArchived with thanks to IEEE Journal of Solid-State Circuitsen
dc.subjectchip multiprocessoren
dc.subjectenergy-efficiencyen
dc.subjectasynchronous interconnecten
dc.subjectgalsen
dc.subjectnetwork-on-chipen
dc.subjectneuromorphic hardwareen
dc.subjectspiking neural networksen
dc.subjectreal-time simulationen
dc.titleSpiNNaker: a 1-W 18-core system-on-chip for massively-parallel neural network simulationen
dc.typeArticleen
dc.contributor.departmentUniversity of Manchesteren
dc.identifier.journalIEEE Journal of Solid-State Circuitsen
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