2.50
Hdl Handle:
http://hdl.handle.net/10547/297903
Title:
SpiNNaker: a multi-core System-on-Chip for massively-parallel neural net simulation
Authors:
Painkras, Eustace; Plana, Luis A.; Garside, Jim; Temple, Steve; Davidson, Simon; Pepper, Jeffrey; Clark, David; Patterson, Cameron; Furber, Steve
Abstract:
The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements.
Citation:
Painkras, E., Plana, L.A., Garside, J. et al, (2012) 'SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation', IEEE Custom Integrated Circuits Conference (CICC), pp.1-4
Publisher:
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date:
2012
URI:
http://hdl.handle.net/10547/297903
DOI:
10.1109/CICC.2012.6330636
Additional Links:
http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6330636
Type:
Conference papers, meetings and proceedings
Language:
en
Appears in Collections:
Centre for Research in Distributed Technologies (CREDIT)

Full metadata record

DC FieldValue Language
dc.contributor.authorPainkras, Eustaceen_GB
dc.contributor.authorPlana, Luis A.en_GB
dc.contributor.authorGarside, Jimen_GB
dc.contributor.authorTemple, Steveen_GB
dc.contributor.authorDavidson, Simonen_GB
dc.contributor.authorPepper, Jeffreyen_GB
dc.contributor.authorClark, Daviden_GB
dc.contributor.authorPatterson, Cameronen_GB
dc.contributor.authorFurber, Steveen_GB
dc.date.accessioned2013-08-12T08:18:04Z-
dc.date.available2013-08-12T08:18:04Z-
dc.date.issued2012-
dc.identifier.citationPainkras, E., Plana, L.A., Garside, J. et al, (2012) 'SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation', IEEE Custom Integrated Circuits Conference (CICC), pp.1-4en_GB
dc.identifier.doi10.1109/CICC.2012.6330636-
dc.identifier.urihttp://hdl.handle.net/10547/297903-
dc.description.abstractThe modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements.en_GB
dc.language.isoenen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCen_GB
dc.relation.urlhttp://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6330636en_GB
dc.subjectdigital simulationen_GB
dc.subjectmicroprocessor chipsen_GB
dc.subjectneural netsen_GB
dc.subjectparallel processingen_GB
dc.subjectsystem-on-chipen_GB
dc.titleSpiNNaker: a multi-core System-on-Chip for massively-parallel neural net simulationen
dc.typeConference papers, meetings and proceedingsen
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