2.50
Hdl Handle:
http://hdl.handle.net/10547/279184
Title:
Scalable communications for a million-core neural processing architecture
Authors:
Patterson, Cameron; Garside, Jim; Painkras, Eustace; Temple, Steve; Plana, Luis A.; Navaridas, Javier; Sharp, Thomas; Furber, Steve
Abstract:
The design of a new high-performance computing platform to model biological neural networks requires scalable, layered communications in both hardware and software. SpiNNaker's hardware is based upon Multi-Processor System-on-Chips (MPSoCs) with flexible, power-efficient, custom communication between processors and chips. The architecture scales from a single 18-processor chip to over 1 million processors and to simulations of billion-neuron, trillion-synapse models, with tens of trillions of neural spike-event packets conveyed each second. The communication networks and overlying protocols are key to the successful operation of the SpiNNaker architecture, designed together to maximise performance and minimise the power demands of the platform. SpiNNaker is a work in progress, having recently reached a major milestone with the delivery of the first MPSoCs. This paper presents the architectural justification, which is now supported by preliminary measured results of silicon performance, indicating that it is indeed scalable to a million-plus processor system.
Citation:
Patterson, C.; Garside, J.; Painkras, E.; Temple, S., Plana, L., Navaridas, J., Sharp, T. and Furber, S. (2012) 'Scalable communications for a million-core neural processing architecture' 72 (11):1507-1520 Journal of Parallel and Distributed Computing
Publisher:
Elsevier
Journal:
Journal of Parallel and Distributed Computing
Issue Date:
2012
URI:
http://hdl.handle.net/10547/279184
DOI:
10.1016/j.jpdc.2012.01.016
Additional Links:
http://linkinghub.elsevier.com/retrieve/pii/S0743731512000287
Type:
Article
Language:
en
ISSN:
07437315
Appears in Collections:
Centre for Research in Distributed Technologies (CREDIT)

Full metadata record

DC FieldValue Language
dc.contributor.authorPatterson, Cameronen_GB
dc.contributor.authorGarside, Jimen_GB
dc.contributor.authorPainkras, Eustaceen_GB
dc.contributor.authorTemple, Steveen_GB
dc.contributor.authorPlana, Luis A.en_GB
dc.contributor.authorNavaridas, Javieren_GB
dc.contributor.authorSharp, Thomasen_GB
dc.contributor.authorFurber, Steveen_GB
dc.date.accessioned2013-04-07T17:04:34Z-
dc.date.available2013-04-07T17:04:34Z-
dc.date.issued2012-
dc.identifier.citationPatterson, C.; Garside, J.; Painkras, E.; Temple, S., Plana, L., Navaridas, J., Sharp, T. and Furber, S. (2012) 'Scalable communications for a million-core neural processing architecture' 72 (11):1507-1520 Journal of Parallel and Distributed Computingen_GB
dc.identifier.issn07437315-
dc.identifier.doi10.1016/j.jpdc.2012.01.016-
dc.identifier.urihttp://hdl.handle.net/10547/279184-
dc.description.abstractThe design of a new high-performance computing platform to model biological neural networks requires scalable, layered communications in both hardware and software. SpiNNaker's hardware is based upon Multi-Processor System-on-Chips (MPSoCs) with flexible, power-efficient, custom communication between processors and chips. The architecture scales from a single 18-processor chip to over 1 million processors and to simulations of billion-neuron, trillion-synapse models, with tens of trillions of neural spike-event packets conveyed each second. The communication networks and overlying protocols are key to the successful operation of the SpiNNaker architecture, designed together to maximise performance and minimise the power demands of the platform. SpiNNaker is a work in progress, having recently reached a major milestone with the delivery of the first MPSoCs. This paper presents the architectural justification, which is now supported by preliminary measured results of silicon performance, indicating that it is indeed scalable to a million-plus processor system.en_GB
dc.language.isoenen
dc.publisherElsevieren_GB
dc.relation.urlhttp://linkinghub.elsevier.com/retrieve/pii/S0743731512000287en_GB
dc.rightsArchived with thanks to Journal of Parallel and Distributed Computingen_GB
dc.subjectGALSen_GB
dc.subjectHPCen_GB
dc.subjectnetwork-on-chipen_GB
dc.titleScalable communications for a million-core neural processing architectureen
dc.typeArticleen
dc.identifier.journalJournal of Parallel and Distributed Computingen_GB
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