2.50
Hdl Handle:
http://hdl.handle.net/10547/279164
Title:
Overview of the SpiNNaker system architecture
Authors:
Furber, Steve B.; Lester, David R.; Plana, Luis A.; Garside, Jim D.; Painkras, Eustace; Temple, Steve; Brown, Andrew D.
Abstract:
SpiNNaker (a contraction of Spiking Neural Network Architecture) is a million-core computing engine whose flagship goal is to be able to simulate the behaviour of aggregates of up to a billion neurons in real time. It consists of an array of ARM9 cores, communicating via packets carried by a custom interconnect fabric. The packets are small (40 or 72 bits), and their transmission is brokered entirely by hardware, giving the overall engine an extremely high bisection bandwidth of over 5 billion packets/s. Three of the principle axioms of parallel machine design -- memory coherence, synchronicity and determinism -- have been discarded in the design without, surprisingly, compromising the ability to perform meaningful computations. A further attribute of the system is the acknowledgement, from the initial design stages, that the sheer size of the implementation will make component failures an inevitable aspect of day-to-day operation, and fault detection and recovery mechanisms have been built into the system at many levels of abstraction. This paper describes the architecture of the machine and outlines the underlying design philosophy; software and applications are to be described in detail elsewhere, and only introduced in passing here as necessary to illuminate the description
Citation:
Furber, S.; Lester, D.; Plana, L.; Garside, J.; Painkras, E.; Temple, S. and Brown, A. (2012) 'Overview of the SpiNNaker System Architecture',1 IEEE Transactions on Computers, 99 pp. 1-14
Publisher:
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Journal:
IEEE Transactions on Computers
Issue Date:
2012
URI:
http://hdl.handle.net/10547/279164
DOI:
10.1109/TC.2012.142
Additional Links:
http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6226357
Type:
Article
Language:
en
ISSN:
0018-9340
Appears in Collections:
Centre for Research in Distributed Technologies (CREDIT)

Full metadata record

DC FieldValue Language
dc.contributor.authorFurber, Steve B.en_GB
dc.contributor.authorLester, David R.en_GB
dc.contributor.authorPlana, Luis A.en_GB
dc.contributor.authorGarside, Jim D.en_GB
dc.contributor.authorPainkras, Eustaceen_GB
dc.contributor.authorTemple, Steveen_GB
dc.contributor.authorBrown, Andrew D.en_GB
dc.date.accessioned2013-04-07T17:21:47Z-
dc.date.available2013-04-07T17:21:47Z-
dc.date.issued2012-
dc.identifier.citationFurber, S.; Lester, D.; Plana, L.; Garside, J.; Painkras, E.; Temple, S. and Brown, A. (2012) 'Overview of the SpiNNaker System Architecture',1 IEEE Transactions on Computers, 99 pp. 1-14en_GB
dc.identifier.issn0018-9340-
dc.identifier.doi10.1109/TC.2012.142-
dc.identifier.urihttp://hdl.handle.net/10547/279164-
dc.description.abstractSpiNNaker (a contraction of Spiking Neural Network Architecture) is a million-core computing engine whose flagship goal is to be able to simulate the behaviour of aggregates of up to a billion neurons in real time. It consists of an array of ARM9 cores, communicating via packets carried by a custom interconnect fabric. The packets are small (40 or 72 bits), and their transmission is brokered entirely by hardware, giving the overall engine an extremely high bisection bandwidth of over 5 billion packets/s. Three of the principle axioms of parallel machine design -- memory coherence, synchronicity and determinism -- have been discarded in the design without, surprisingly, compromising the ability to perform meaningful computations. A further attribute of the system is the acknowledgement, from the initial design stages, that the sheer size of the implementation will make component failures an inevitable aspect of day-to-day operation, and fault detection and recovery mechanisms have been built into the system at many levels of abstraction. This paper describes the architecture of the machine and outlines the underlying design philosophy; software and applications are to be described in detail elsewhere, and only introduced in passing here as necessary to illuminate the descriptionen_GB
dc.language.isoenen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCen_GB
dc.relation.urlhttp://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6226357en_GB
dc.rightsArchived with thanks to IEEE Transactions on Computersen_GB
dc.subjectinterconnection architecturesen_GB
dc.titleOverview of the SpiNNaker system architectureen
dc.typeArticleen
dc.identifier.journalIEEE Transactions on Computersen_GB
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