Off-loading application controlled data prefetching in numerical codes for multi-core processors

2.50
Hdl Handle:
http://hdl.handle.net/10547/251814
Title:
Off-loading application controlled data prefetching in numerical codes for multi-core processors
Authors:
Trinitis, Carsten; Weidendorfer, Josef
Abstract:
An important issue when designing numerical code in High Performance Computing is cache optimisation in order to exploit the performance potential of a given target architecture. This includes techniques to improve memory access locality as well as prefetching. Inherent algorithm constrains often limit the first approach, which typically uses a blocking technique. While there exist automatic prefetching mechanisms in hardware and/or compilers, they can not complement blocking with additional prefetching. We provide an infrastructure for off-loading application controlled prefetching on a chip multiprocessor, allowing to further improve numerical code already optimised by standard cache optimisation. Clear benefits are shown for real workloads on existing hardware.
Citation:
Weidendorfer, J., Trinitis, C. (2008) 'Off-loading application controlled data prefetching in numerical codes for multicore processors', 4 (1): 22-28, Int. J. of Computational Science and Engineering
Publisher:
Inderscience
Journal:
International Journal of Computational Science and Engineering
Issue Date:
Nov-2008
URI:
http://hdl.handle.net/10547/251814
Additional Links:
http://dl.acm.org/citation.cfm?id=1457171
Type:
Article
Language:
en
ISSN:
1742-7185
EISSN:
1742-7193
Appears in Collections:
Centre for Research in Distributed Technologies (CREDIT)

Full metadata record

DC FieldValue Language
dc.contributor.authorTrinitis, Carstenen_GB
dc.contributor.authorWeidendorfer, Josefen_GB
dc.date.accessioned2012-11-12T13:29:24Z-
dc.date.available2012-11-12T13:29:24Z-
dc.date.issued2008-11-
dc.identifier.citationWeidendorfer, J., Trinitis, C. (2008) 'Off-loading application controlled data prefetching in numerical codes for multicore processors', 4 (1): 22-28, Int. J. of Computational Science and Engineeringen_GB
dc.identifier.issn1742-7185-
dc.identifier.urihttp://hdl.handle.net/10547/251814-
dc.description.abstractAn important issue when designing numerical code in High Performance Computing is cache optimisation in order to exploit the performance potential of a given target architecture. This includes techniques to improve memory access locality as well as prefetching. Inherent algorithm constrains often limit the first approach, which typically uses a blocking technique. While there exist automatic prefetching mechanisms in hardware and/or compilers, they can not complement blocking with additional prefetching. We provide an infrastructure for off-loading application controlled prefetching on a chip multiprocessor, allowing to further improve numerical code already optimised by standard cache optimisation. Clear benefits are shown for real workloads on existing hardware.en_GB
dc.language.isoenen
dc.publisherInderscienceen_GB
dc.relation.urlhttp://dl.acm.org/citation.cfm?id=1457171en_GB
dc.titleOff-loading application controlled data prefetching in numerical codes for multi-core processorsen
dc.typeArticleen
dc.identifier.eissn1742-7193-
dc.identifier.journalInternational Journal of Computational Science and Engineeringen_GB
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