2.50
Hdl Handle:
http://hdl.handle.net/10547/250939
Title:
Sparse matrix operations on several multi-core architectures
Authors:
Trinitis, Carsten; Küstner, Tilman; Weidendorfer, Josef; Smajic, Jasmin
Abstract:
This paper compares various contemporary multicore-based microprocessor architectures from different vendors with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix decomposition is used as a benchmark application. The example matrix used in the experiments comes from an electrical engineering application, where numerical simulation of physical processes plays an important role in the design of industrial products. Within this context, thread-to-core pinning and cache optimization are two important aspects which are investigated in more detail.
Citation:
Trinitis, C. et al (2010) 'Sparse matrix operations on several multi-core architectures' The Journal of Supercomputing 57 (2):132-140
Publisher:
SpringerLink
Journal:
The Journal of Supercomputing
Issue Date:
2010
URI:
http://hdl.handle.net/10547/250939
DOI:
10.1007/s11227-010-0428-9
Additional Links:
http://www.springerlink.com/index/10.1007/s11227-010-0428-9
Type:
Article
Language:
en
Description:
From the issue entitled "Special Issue on Parallel Computing Technologies"
ISSN:
0920-8542; 1573-0484
Appears in Collections:
Centre for Research in Distributed Technologies (CREDIT)

Full metadata record

DC FieldValue Language
dc.contributor.authorTrinitis, Carstenen_GB
dc.contributor.authorKüstner, Tilmanen_GB
dc.contributor.authorWeidendorfer, Josefen_GB
dc.contributor.authorSmajic, Jasminen_GB
dc.date.accessioned2012-11-05T09:45:43Zen
dc.date.available2012-11-05T09:45:43Zen
dc.date.issued2010en
dc.identifier.citationTrinitis, C. et al (2010) 'Sparse matrix operations on several multi-core architectures' The Journal of Supercomputing 57 (2):132-140en_GB
dc.identifier.issn0920-8542en
dc.identifier.issn1573-0484en
dc.identifier.doi10.1007/s11227-010-0428-9en
dc.identifier.urihttp://hdl.handle.net/10547/250939en
dc.descriptionFrom the issue entitled "Special Issue on Parallel Computing Technologies"en_GB
dc.description.abstractThis paper compares various contemporary multicore-based microprocessor architectures from different vendors with different memory interconnects regarding performance, speedup, and parallel efficiency. Sparse matrix decomposition is used as a benchmark application. The example matrix used in the experiments comes from an electrical engineering application, where numerical simulation of physical processes plays an important role in the design of industrial products. Within this context, thread-to-core pinning and cache optimization are two important aspects which are investigated in more detail.en_GB
dc.language.isoenen
dc.publisherSpringerLinken_GB
dc.relation.urlhttp://www.springerlink.com/index/10.1007/s11227-010-0428-9en_GB
dc.subjectmulticoreen_GB
dc.subjectpinningen_GB
dc.subjectcache optimizationen_GB
dc.subjectperformance optimizationen_GB
dc.subjectsparse matricesen_GB
dc.titleSparse matrix operations on several multi-core architecturesen
dc.typeArticleen
dc.identifier.journalThe Journal of Supercomputingen_GB
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